CDADIC - Projects, 2005-2006

Multiple-input multiple-output (MIMO) systems can achieve higher data rates through spatial multiplexing or greater link reliability through diversity. The primary need for next-generation radios is adaptivity based on cognition of the environment. Accordingly, the focus of this research is to realize a transceiver architecture that is able to adaptively select between a high data rate and high reliability configuration. This will be demonstrated through implementing a 4-antenna hybrid diversity/spatial-multiplexing transmitter utilizing the Alamouti-style space-time block codes (STBC). The transmitter is built around a direct conversion core while realizing the conjugation and inversion function in the digital domain. The combination of the diversity and spatial multiplexing will occur in the antenna configuration; three of the antennas will be devoted to diversity while the remaining one will be devoted to spatial multiplexing. Finally, the total transmitted power can be the same as in a single-antenna transmitter; hence, a multi-antenna transmitter radiates lower power from each antenna, which allows for power amplifiers with lower peak power output and higher efficiency. Benefits to Industry Members: The Alamouti diversity technique has been incorporated into the 3G cellular standard. Other standards such as the 3G High-Speed Packet Data Access (HSDPA) and the IEEE 802.16 (WiMAX) envision extensive use of diversity-type MIMO systems. Since MIMO communications is set for burgeoning growth in the near-term, the results of this research will be applicable to next-generation transceivers. Other offshoots of this research will include innovative transmitter architectures and circuit topologies that may find application in conventional single-channel radios.

The increasing complexity and performance requirements of analog systems along within the constraints of scaled CMOS technology, including reduced supply voltage and device output impedance, give rise to further investigation of precision sub-1 V voltage reference design. As a continuation of last year’s effort, UT will focus on developing an improved switch-capacitor sub-1 V bandgap voltage reference (BGR) with lower output noise. Also, UT will investigate using a low-turn-on voltage diode, e.g. Schottky diode, to further reduce the allowable BGR supply voltage. An additional test chip will be submitted and fully characterized. It is expected that the research results from this work would be immediately applicable to commercial applications. Benefits to Industry Members: The sub-1 V BGR resulting from this effort should find immediate application in the commercial sector, especially for 90 nm and lower feature size processes. The effectiveness of noise cancellation applied in the switch-capacitor BGR will be verified and its low noise potential will be exploited, which could directly impact the achievable accuracy of data conversion systems in ultra deep sub-micron processes. The Schottky diode characterization effort and possibly Schottky-diode-based voltage reference design and development can also provide significant contributions to system-on-a-chip (SoC) applications in ultra deep sub-micron processes.

Conventional equalized serial links use multi-phase timing architectures for multi-tap equalizers. However, as data rates continue to increase and the metrics of area/power continue to decrease, such equalization techniques become less efficient and more complex to build with limited effectiveness as the number of taps increases. One possible alternative to these problems is to build a high sampling rate, low resolution A/D converter, where the channel equalization techniques are implemented in the digital domain, resulting in lower power, higher scalability and greater flexibility. This research will explore the theoretical and practical constraints of future high speed equalizers in serial links, and contrast these design issues with building a high speed, low resolution ADC. A new down-sampling demultiplexing architecture, with precision clock front-end sampling, will be introduced for this high sampling rate, low resolution ADC (> 20GS/s, 4-6 bits), achieving orders of magnitude less power and area than the current state-of-the-art ADCs. The performance of this high speed ADC, along with back-end digital equalization, will be compared with the traditional mixed-signal equalizers for various channel types, giving insight into the design of future high speed serial links in lossy channels. Benefits to Industry Partners: This research will help member companies interested in serial link circuits understand the practicality of implementing an ADC receiver structure for future links, which may have advantages in regards to power, speed, flexibility, and scalability compared to conventional equalizer approaches. This work has direct impact on member companies Freescale, Mindspeed, and Texas Instruments, who are very involved with serial link development. Beyond this immediate area, this work is very applicable to other mixed-signal front-end research. For example, high sampling rate, low resolution A/D converters with low power dissipation are crucial for ultra-wideband radio, 10G Ethernet over twisted pair, and others. In addition to the above mentioned companies, Analog Devices, Boeing, AFRL, Qualcomm and SRC would find this work useful.

Last year, we have demonstrated a 14-bit 5MS/s continuous-time ∆-Σ A/D converter. It was designed, fabricated and tested and it demonstrated excellent performance. This design achieved 81dB peak SNR and 85dB dynamic range with a 12X oversampling ratio while dissipating only 50mW of power. It used a 4-bit background calibrated DAC with a 5th-order modulator. Various non-ideal effects degrade this performance and we have addressed them in the design while using a 0.25um CMOS process. This year, we propose to increase the resolution to 16b while still achieving 5MS/s with a continuous-time delta-sigma ADC. We will target a 90nm or smaller process. Much of our emphasis is on developing a novel DAC calibration method and developing low power and low voltage circuit approaches.Benefits to Industry Partners: The techniques being developed in this project are applicable to other mixed-signal circuits. Additionally, other novel circuit techniques are expected to be developed through this design.

Advancements in multigigahertz wired and wireless communication technology catering to high data rate requirements prompt the investigation of innovative low cost, low power and low voltage high-speed mixed signal circuits. In the future, a universal RF transceiver capable of covering multiband and multimode operations will be desirable for wired and wireless hybrid network. In both wired and wireless communication the communication bandwidth is heavily dependent on the quality of the signal source or the frequency synthesizer; however, PLLs come with their own unique set of challenges. They inherently take a long time to lock, and most techniques sacrifice performance to help PLLs to lock quickly. This problem puts wireless applications in an unenviable position, as they are driven by low power, high performance operation. Low-power constraints demand that PLLs be turned off during inactivity, but then require that they lock quickly when turned back on. Therefore novel fast locking low power PLLs are driven by the tight demand of state-of-the art multiband wideband applications. For fast hopping wireless systems as well as wired transceivers, the fast locking PLL is desirable for low power application and for reduced data latency. In the following research period, our research will have two major thrusts: (i) continued research on improving VCO phase noise and the development of build a wide tuning range VCO and a multiband VCO with high FOM factor and (ii) fast locking low jitter PLL with ultra low power prescaler/divider and low phase noise VCOs covering 10 Gbps (OC192) and 3.125 Gbps (XAUI) wired transceivers, 2.5 GHz, 3.5 GHz and 5.8 GHz wireless transceivers covering IEEE 802.11a/b/g, WiMAX (IEEE802.16), and HiperMan standards. Benefits to Industry Partners: Fast locking and low jitter PLL will help mitigate performance degradation that in many cases is the bottleneck for DCR and image reject receivers. Additionally a high performance PLL translates into low rms jitter in the wired communication which helps wired transceiver meet jitter tolerance and jitter generation and improves the BER rates. This research will greatly benefit member companies in transceiver applications as well as companies interested in clock generation and PLLs.

This project will continue to investigate high-speed data converter circuits in SiGe BiCMOS technology. The focus of the research will be to increase accuracy of analog-to-digital converters (ADCs) with conversion rates in the 1 GSps to 10 GSps range. These ADCs have applications in high-bandwidth communications and instrumentation. The goals for our ADCs are 12-bit accuracy at 1 GSps and later 10 bits at 5 GSps. In many Nyquist ADCs, the initial track and hold amplifiers (THAs) determine the overall linearity of the ADC. THAs relax the timing requirements for subsequent quantizers but non-ideal behavior causes distortion of the analog input signal, many times limiting performance of the ADC. We designed and laid out many versions of THAs using different architectures and various compensation techniques with simulated accuracy of about 11-bits at 1 GSps. We expect to receive fabricated die in the first week of July. We have also completed testing building blocks needed for pipelined or successive approximation ADCs. These include a 4-bit flash converter, a 4-bit DAC and a difference amplifier. This year we will characterize the 11 THA versions, combine an improved interleaving THA with updated versions of the ADC building blocks into a 12-bit ADC at 1 GSps. We will investigate interleaving THA designs that require lower bandwidth and promise higher signal-to-noise ratio (SNR). Interleaving also relaxes the timing constraints on the ADC building blocks. Methods will be investigated to combine the interleaved signals so that two complete channels are not required, saving area and reducing power dissipation. Although interleaving may improve the accuracy of the THA, further research is needed to realize full 12-bit accuracy at 1 GSps. We will investigate approaches to increase SNR, which is limiting the accuracy in the current designs. One approach is to use FET switches driven with fast bipolar circuits. The amplifiers in the signal path promise to have lower-noise. Another approach adds low gain amplifiers before the THA to increase the SNR. Adjusting the DAC output levels to compensate for non-linearities in the THA and difference amplifier will also be included in the ADC. Fabrication and characterization of a 12-bit ADC at 1 GSps will be completed in the upcoming year. Benefits to Industry Partners: Many member companies use ADC circuits in their products or provide ADC products. This work will help to increase understanding of the effect different approaches, architectures and compensation techniques have on the performance of high-speed high-accuracy THAs and ADCs in SiGe technology. An advantage of using SiGe BiCMOS technology for ADCs over other high-speed technologies, such as InP and GaAs HBT, is the availability of low-power CMOS with high-integration levels. This opens up freedom to provide extensive calibration and error correction on-chip to improve accuracy without significant degradation in yield or increase in power dissipation. The ADCs can also be used with other circuits for system-on-chip applications. Increased accuracy of high-speed ADCs will result from architectures, methods and techniques developed in this work.

Phase-locked loops (PLLs) are key building blocks of frequency synthesizers and clock generators and they are used in nearly all analog, digital, and RF ICs. In all these applications there are stringent requirements on the phase-noise/jitter performance of PLLs. These requirements are difficult to meet in the deep submicron digital CMOS processes of the near future. Therefore, it is necessary to investigate circuits and architectures that result in PLLs that are insensitive to both the process variations and noise in scaled CMOS technologies. This project addresses the design of multi-GHz frequency synthesizers in deep submicron digital processes. Low voltage design techniques for noise tolerant PLLs and frequency synthesizers will be developed. Self-calibration methods will also be developed to tune out process/temperature and voltage variations yielding a robust design. The final outcome of this work will be a set of design techniques for low voltage PLLs in very deep submicron digital CMOS processes that are insensitive to process variations and noise. Benefits to Industry Partners: Design techniques that will be developed in this project will lead to process and noise tolerant frequency synthesizers in deep submicron digital CMOS processes, while architectural developments can be generally applied to all IC processes such as BiCMOS, SiGe or SOI. New circuits and architectures will be developed and combined with self-calibration methods. The design will also include novel tuning techniques that expand the frequency range of operation by digital control. Frequency synthesizers are an important building block for RF, communication, and signal processing circuits, hence, this work will have a significant impact.

During the past year, we have been designing analog-to-digital data converters (ADCs) constructed from several (2»16) delta-sigma converter cells. The cells share a common input, and their outputs are combined to get the overall digital output. This design provides the greater flexibility in trading off the accuracy for reduced power dissipation. The trade-off between accuracy and reduced power dissipation is accomplished through turning on and off a different number of delta-sigma converter cells. During the course of the research, we have discovered a novel scheme which substantially outperforms the current design. In particular, when the quantization errors are coupled from cell to cell, the overall SNR can be improved significantly. Thus in this research, we shall study the optimum design of the ADCs and their coupling circuits, and develop high-speed/high-accuracy delta-sigma ADCs based on the new design technique. Benefits to Industry Partners: We expect that the novel design approach will enable the realization of highly flexible data converters, both in stand-alone and embedded applications. The noise-coupling method promises to lead to higher performance for a given chip area and power dissipation, in addition to the increased flexibility afforded by the multicell construction.

We shall develop design theory and techniques for multiplexed incremental data converters (IDCs), and design a prototype device implementing our theoretical results. There are many applications for such a device in instrumentation and measurement (I&M), as well as in the biomedical field. The proposed research will offer a novel and highly accurate method for data acquisition in multi-channel I&M systems. The main goal of the project is to establish a design protocol for multiplexed data acquisition devices based on IDC principles. IDCs can perform extremely accurate data conversion (over 20 bit accuracy has been achieved) for single-channel dc signals. We shall extend the operation to multi-channel applications, with time-varying measurands. We shall find optimum architectures as well as theoretical analysis techniques, and verify these by the development of a test device. Benefits to Industry Partners: The proposed research will offer a novel and highly accurate method for data acquisition in multi-channel I&M systems.